A DIMM (Dual Inline Memory Module) has card edge connectors for transmitting and receiving electric signals externally where electric signals are assigned to the front and back of the board (one row each), and various kinds of products such as DDR (Double Data Rate), SDRAM (Synchronous DRAM), and 184-pin DIMM (400 MHz/256 MB) have been on the market. A DIMM is used for PCs and workstations, for instance, and mounted on the board perpendicularly using a DIMM socket.
FIG. 5 is a drawing showing an example of the structure of a conventional memory module (multidrop system). In reference to FIG. 5, first module substrates 10, each of which has multiple DRAMs 11 (eight of them, for example), are inserted into sockets 30 soldered to a motherboard 40. In the example shown in FIG. 5, eight of the first module substrates 10 are mounted, and the eight first modules 101 through 108 are bus-connected and connected to a LSI 60 for controlling DRAM controllers. The controller LSI 60 is connected to a CPU, not shown in the drawing, on the motherboard 40. Hereinafter, the structure comprising the first module substrates 10 and the DRAMs 11 shown in FIG. 5 is called the first module. The first module corresponds to the above-mentioned DIMM. Further, the first module substrates 101 through 108 are referred to as the first module substrate 10 when a number is not specified.
In the case of the structure shown in FIG. 5, when the data transfer rate reaches high-speed, signal deterioration at the pins of the bus-connected first modules 10 becomes apparent. Furthermore, when the data transfer rate of each pin of the first modules 10 exceeds, for instance, 500 Mbps (megabits per second), no more than two first modules can be connected.
If a structure where multiple first modules are parallel-connected is employed as a countermeasure to the problem of the bus structure shown in FIG. 5, the numbers of the wiring lines and wiring layers on the motherboard and the wiring constraint increase. For instance, if eight of the first modules are parallel-connected, the motherboard will require not less than eight layers, resulting in a cost increase. Therefore, it is difficult to increase capacity.
For instance, as means for reducing the number of the wiring lines on the motherboard, a structure where the first module substrates are cascade-connected (daisy chain method), shown in FIG. 6, is known. The data from the controller LSI 60 is transferred via the first module substrates one after another, and reaches its ultimate destination, the DRAM. Also, the output from the DRAM 11 of the rightmost first module substrate 108 is inputted into the controller LSI 60 after passing through the first module substrates 107 through 101 one after another.
Furthermore, in order to reduce the number of the pins on the first module substrates and increase the data transfer speed, a technique of increasing the speed of the input/output of the DRAM by multiplexing it is also known. (Refer to Non-Patent Document 1, for example.) However, in the case of the above-mentioned technique where the input/output of the DRAM is multiplexed to increase its speed, for instance, in order for the data to pass through all the eight first module substrates 101 to 108, each first module substrate requires input/output pins. In this case, the actual overall data transfer speed is ½ at the first module compared to the data transfer speed of the interface of each module and the number of the pins on the first module since the input and output of the DRAM are multiplexed. Therefore, the test cost for the interface of the first module is doubled. (For example, the test time is doubled.)
Further, in the structure shown in FIG. 6, the more the number of the cascade-connected first module substrates 10 increases, the more the data transfer rate per interface decreases, divided by the number of the cascade-connected module substrates.
For instance, in the case where the first modules have:                10 incoming send/receive channels (send: 2 pins/1 channel, receive: 2 pins/1 channel, a total of 40 pins)        10 outgoing send/receive channels (send: 2 pins/1 channel, receive: 2 pins/1 channel, a total of 40 pins)        a data rate of 2 Gbps per channel        Eight modules connected        
The overall number of the high-speed interfaces is (10+10)×8=160 send/receive channels, and the overall data transfer speed is 10×2=20 Gbps.
Furthermore, in the case of the structure shown in FIG. 6, since it is a daisy-chain connection system, the bigger the number of the first modules connected is, the more the latency increases.
Further, a structure where a controller multiplexes the data of multiple SDRAMs and outputs it to a data I/O bus, and an address and data from a processor are demultiplexed and supplied to the SDRAM is described in Patent Document 1.
[Patent Document 1]
Japanese Patent Kokai Publication JP-A-10-340224 (FIGS. 1 and 5) (corresponding U.S. Pat. No. 5,870,350A)
[Non-Patent Document 1]
Joseph Kennedy et al., “A 2 Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems,” IEEE International Solid-State Circuits Conference ISSCC/SESSION 11/DRAM/11.8, pp. 214-215, February 2004.
The entire disclosures of Patent Document 1 and Non-Patent Document 1 are incorporated herein by reference thereto.